Hardware-Aware Compiler Routing on Superconducting Processors: Depth-Fidelity Tradeoffs and Latency Limits in Physical Dynamic Circuits
We evaluate whether a pre-QPU calibration-aware compiler decision model can accurately predict the winning implementation for long-range two-qubit entangling gates on current superconducting hardware. Testing across three physical distance cohorts (3, 7, and 13 hops) on a 156-qubit IBM Heron processor (ibm_marrakesh, Job ID da1t22mg52gs73cm31i0, 18,432 physical shots), we compare unitary SWAP-based routing against dynamic mid-circuit measurement and classical feed-forward routing. While dynamic routing maintained a strictly constant two-qubit gate depth (depth = 2 vs unitary depths of 13, 37, and 73), unitary routing achieved higher Bell-state fidelity on SHORT (0.8618 vs 0.8209) and MEDIUM (0.8135 vs 0.7651) separations. At 13 hops (LONG), the fidelity difference was statistically inconclusive (0.6669 vs 0.6356, 95% CI [-0.0630, +0.0005]), leaving the physical routing crossover unresolved. The frozen pre-QPU cost model correctly predicted both conclusive routing winners (2/2) based partly on a predeclared feed-forward latency penalty heuristic (λ = 0.012). We present comprehensive numerical audits, sensitivity analyses, and strict scientific claim boundaries.
1. Research Question
In planar superconducting quantum architectures with restricted nearest-neighbor coupling topologies (such as the heavy-hex lattice of IBM Heron processors), executing long-range entangling operations between distant qubits is a primary source of circuit overhead.
Quantum compilers have two primary paradigms for non-local routing:
- Unitary SWAP-Based Routing: Sequentially swapping quantum states along a physical coupling path. Gate depth and two-qubit error accumulation scale linearly with physical separation.
- Dynamic Circuit Routing (MCM + Feed-Forward): Using an ancilla chain with mid-circuit measurements and classical feed-forward corrections to teleport entanglement in constant two-qubit gate depth (depth = 2) regardless of distance.
Core Research Question: Can a pre-QPU calibration-aware compiler decision model choose between unitary SWAP routing and dynamic feed-forward routing to maximize physical Bell-state fidelity on current NISQ hardware across different topological distances?
2. Known Prior Art & Scientific Claim Boundaries
To maintain scientific integrity and prevent exaggerated claims, we explicitly delineate the boundary between established prior art and Q-Psi's evaluated contribution:
Q-Psi does not claim invention of dynamic circuits, mid-circuit measurement, classical feed-forward, gate teleportation, measurement-based entangling gates, or SWAP routing algorithms.
The contribution evaluated in this study is a frozen compiler-oriented routing-decision protocol that combines active calibration metrics with a mid-circuit latency model, along with its empirical physical-QPU validation across a 3-distance cohort on IBM Heron hardware.
3. Hardware Setup & Two Routing Implementations
The experiment was executed on ibm_marrakesh (IBM Heron r2, 156 programmable qubits) under Job ID da1t22mg52gs73cm31i0, consuming 10.5 seconds of physical QPU runtime across 18 distinct circuits (1,024 shots each; 18,432 total physical shots).
We evaluated three topological separations along an authentic linear coupling chain on the processor:
- SHORT: 3 physical hops
- MEDIUM: 7 physical hops
- LONG: 13 physical hops
Depth Comparison
| Separation Cohort | Topological Hops | Unitary 2Q Depth | Dynamic 2Q Depth | Depth Advantage |
|---|---|---|---|---|
| SHORT | 3 hops | 13 | 2 | 6.5× reduction |
| MEDIUM | 7 hops | 37 | 2 | 18.5× reduction |
| LONG | 13 hops | 73 | 2 | 36.5× reduction |
4. Physical Bell Fidelity & Empirical Results
Each circuit prepared a target Bell state |Φ+〉 = (|00〉 + |11〉) / √2 between the distant control and target qubits. State fidelity was measured via quantum state tomography and parity observables.
| Cohort | Unitary Bell Fidelity (95% CI) | Dynamic Bell Fidelity (95% CI) | ΔF = F_D - F_U (95% CI) | Hardware Winner |
|---|---|---|---|---|
| SHORT (3H) | 0.8618 [0.8462, 0.8770] | 0.8209 [0.8032, 0.8379] | -0.0409 [-0.0635, -0.0181] | UNITARY_WIN |
| MEDIUM (7H) | 0.8135 [0.7959, 0.8311] | 0.7651 [0.7461, 0.7842] | -0.0485 [-0.0747, -0.0225] | UNITARY_WIN |
| LONG (13H) | 0.6669 [0.6450, 0.6890] | 0.6356 [0.6128, 0.6582] | -0.0314 [-0.0630, +0.0005] | INCONCLUSIVE |
- Constant Depth Is Not Automatically Better Fidelity: Even though dynamic circuits maintained depth 2 across all cohorts, unitary SWAP routing achieved statistically superior Bell fidelity at 3 and 7 hops on current Heron hardware.
- Physical Crossover Remained Unresolved: At 13 hops, the 95% confidence interval for ΔF spans zero. The physical crossover was not resolved, and we do not extrapolate an untested crossover distance.
5. Pre-QPU Model Predictions & Confirmation Score
Prior to QPU execution, the calibration-aware cost model evaluated the target coupling paths using frozen calibration snapshots.
| Distance Cohort | Frozen Pre-QPU Prediction | Physical Conclusive Outcome | Prediction Confirmed? |
|---|---|---|---|
| SHORT (3 hops) | UNITARY | UNITARY_WIN | CONFIRMED |
| MEDIUM (7 hops) | UNITARY | UNITARY_WIN | CONFIRMED |
| LONG (13 hops) | UNITARY | INCONCLUSIVE | NOT COUNTED |
Model Prediction Confirmation Score: 2 / 2 statistically conclusive tested distances (LONG is inconclusive and excluded from confirmation count).
6. Critical Qualification: Feedforward Latency Heuristic & Sensitivity
The pre-QPU cost model incorporated an explicit mid-circuit feed-forward latency penalty coefficient:
Audit Classification: PREDECLARED_HEURISTIC. While frozen prior to physical execution, this parameter was not directly extracted from an active real-time backend API calibration field.
Sensitivity Analysis Across λ
| Latency Penalty (λ) | SHORT (3H) | MEDIUM (7H) | LONG (13H) | Model Decision |
|---|---|---|---|---|
| λ = 0.000 (Zero penalty) | DYNAMIC | DYNAMIC | DYNAMIC | Uncalibrated baseline |
| λ = 0.003 | DYNAMIC | DYNAMIC | DYNAMIC | Dynamic preferred |
| λ = 0.006 | DYNAMIC | DYNAMIC | UNITARY | Partial shift |
| λ = 0.009 | DYNAMIC | UNITARY | UNITARY | Partial shift |
| λ = 0.012 (Frozen Model) | UNITARY | UNITARY | UNITARY | 2/2 Conclusive Matches |
| λ = 0.015 | UNITARY | UNITARY | UNITARY | Stable Unitary |
| λ = 0.020 | UNITARY | UNITARY | UNITARY | Stable Unitary |
Robustness Classification: PARTIAL. The model successfully matches physical outcomes when λ ≥ 0.012, demonstrating that modeling mid-circuit measurement and classical feed-forward latency is essential on modern hardware.
7. Cryptographic Audit & Freeze Integrity
8. Authorized Public Claim & Excluded Statements
“On a frozen three-distance physical IBM Heron benchmark, Q-Psi's pre-QPU routing model correctly predicted the winning long-range CNOT implementation on both statistically conclusive tested distances. The dynamic implementation maintained constant two-qubit depth, but did not achieve higher Bell-state fidelity within the tested cohort. The routing crossover remained unresolved, and the predictive result depends partly on a predeclared mid-circuit latency heuristic; no general predictive-compiler or quantum-advantage claim is made.”
- NO Quantum Advantage: This experiment does not claim quantum advantage.
- NO Dynamic Circuit Superiority: Dynamic circuits did not outperform unitary SWAP routing in measured physical fidelity.
- NO Crossover Resolution: The physical crossover was not observed or resolved.
- NO General Predictive Compiler: Findings are bounded to the tested three-distance benchmark.