Reusing Physical Qubits with Compiler Liveness Analysis on IBM Heron

1. The Register Width Problem in NISQ Hardware

In quantum algorithm design, logical qubits are traditionally assumed to persist for the entire duration of a circuit. However, on physical quantum hardware, maintaining idle qubits incurs continuous decoherence ($T_1/T_2$ decay) and spectator cross-talk errors.

By performing static liveness analysis on the compiler's intermediate representation, the Q-Psi compiler identifies when a logical qubit's information has been fully extracted or measured. The physical slot is then reset ($|0\rangle$) and reassigned to a new logical wire.

2. Experimental Execution on IBM Marrakesh

We evaluated 6 streaming benchmark circuits on IBM Heron r2 (24,576 shots total). Logical register requirements ranged from 8 to 16 qubits:

3. Non-Inferiority Verification

Reducing physical register width is only useful if observable output fidelity is preserved. In 4 out of 6 cases, the reused circuit achieved strictly lower observable RMSE than the uncompressed circuit, because eliminating idle qubits reduced cumulative $T_1$ decoherence. All 6 cases satisfied the pre-declared non-inferiority margin ($\epsilon = 0.05$).

4. Structural Claim Boundary